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[AK4340] ms0501-e-01 2010/09 - 1 - general description the AK4340 offers the ideal featur es for consumer systems that require a 2vrms audio output. using akm's multi bit architecture for its modulator t he AK4340 delivers a wide dynamic range while preserving linearity for improved thd+n perform ance. the AK4340 integrates the sw itched capacitor filter (scf) increasing performance for systems with excessive clock jitter. the 24 bit word length and 192khz sampling rate make this part ideal for a wide range of applications including set- top-box, dvd-audio. the AK4340 is offered in a spac e saving 16pin tssop package. features ? sampling rate ranging from 8khz to 192khz ? 128 times oversampling (normal speed mode) ? 64 times oversampling (double speed mode) ? 32 times oversampling (quad speed mode) ? 24-bit 8 times fir digital filter ? switched capacitor filter with high tolerance to clock jitter ? on chip buffer with 2vrms single-ended output ? digital de-emphasis filter: 32khz, 44.1khz or 48khz ? soft mute function ? digital attenuator (linear 256 step) ? audio interface format: 24bit msb justified, 24/20/16 lsb justified or i 2 s compatible ? master clock: 256fs, 384fs, 512fs, 768fs or 1152fs (normal speed mode) 128fs, 192fs, 256fs or 512fs (double speed mode) 128fs or 192fs (quad speed mode) ? thd+n: -90db ? dynamic range: 106db ? power supply: +4.5v to +5.5v (dac), - 4.5v to - 13.2v (output buffer) ? ta = - 20 to 85 c ? package: 16pin tssop (6.4mm x 5.0mm) 192khz 24-bit stereo ? dac with 2vrms output AK4340 lrc k bick sdti a udio data interface mclk pdn ? modulator a outl 8x interpolator scf lpf a outr v dd v ss de-emphasis control p/s p interface cloc k divider smute/csn acks/ccl k dif0/cdti ? modulator 8x interpolator hvee scf lpf at t at t gain
[AK4340] ms0501-e-01 2010/09 - 2 - ordering guide AK4340et -20 +85 c 16pin tssop (0.65mm pitch) akd4340 evaluation board for AK4340 pin layout 1 mclk lrck bick smute/csn acks/cclk dif0/cdti top view 2 3 4 5 6 7 8 gain nc vss vdd hvee a outl a outr p/s 16 15 14 13 12 11 10 9 pdn sdti
[AK4340] ms0501-e-01 2010/09 - 3 - pin / function no. pin name i/o function 1 mclk i master clock input pin an external ttl clock s hould be input on this pin. 2 bick i audio serial data clock pin 3 sdti i audio serial data input pin 4 lrck i l/r clock pin 5 pdn i power-down mode pin when at ?l?, the AK4340 is in the power-down mode and is held in reset. the AK4340 must be reset once upon power-up. smute i soft mute pin in parallel control mode ?h?: enable, ?l?: disable 6 csn i chip select pin in serial control mode acks i auto setting mode pin in parallel control mode ?l?: manual setting mode, ?h?: auto setting mode 7 cclk i control data clock pin in serial control mode dif0 i audio data interface format pi n in parallel control mode 8 cdti i control data input pin in serial control mode 9 aoutr o rch analog output pin 10 aoutl o lch analog output pin 11 hvee - output buffer negative power supply pin normally connected to vss with a 0.1 f ceramic capacitor in parallel with a 10 f electrolytic cap. 12 vss - ground pin 13 vdd - dac power supply pin 14 p/s i parallel/serial select pin (internal pull-up pin) ?l?: serial control mode, ?h?: parallel control mode 15 nc - no connect no internal banding (note) 16 gain i output gain select pin ?l?: 0db, ?h?: +1.94db note: do not allow digital input pins except pull-up pin to float. note: pin no.15 (nc) has no internal bonding and can be left open, connected gnd or vdd.
[AK4340] ms0501-e-01 2010/09 - 4 - absolute maximum ratings (vss=0v; note 1 ) parameter symbol min max units power supply dac output buffer vdd hvee -0.3 -14.0 +6.0 0.3 v v input current (any pins except for supplies) iin - 10 ma input voltage vind -0.3 vdd+0.3 v ambient operating temperature ta -20 85 c storage temperature tstg -65 150 c note 1. all voltages with respect to ground. warning: operation at or beyond these limits may results in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (vss=0v; note 1) parameter symbol min typ max units power supply dac output buffer vdd hvee +4.5 -13.2 +5.0 -5.0 +5.5 -4.5 v v note 1. all voltages with respect to ground. *akm assumes no responsibility for the usage beyond the conditions in this datasheet.
[AK4340] ms0501-e-01 2010/09 - 5 - analog characteristics (ta=25 c; vdd=+5.0vv; hvee=-5.0v; fs=44.1khz; bick= 64fs; signal frequency=1khz; 24bit input data; measurement frequency=20hz 20khz; r l 5k ; unless otherwise specified) parameter min typ max units resolution 24 bits dynamic characteristics ( note 2) fs=44.1khz bw=20khz 0dbfs -60dbfs -90 -42 -84 - db db fs=96khz bw=40khz 0dbfs -60dbfs -90 -39 - - db db thd+n fs=192khz bw=40khz 0dbfs -60dbfs -90 -39 - - db db dynamic range (-60dbfs with a-weighted) ( note 3 ) 100 106 db s/n (a-weighted) ( note 4 ) 100 106 db interchannel isolation (1khz) 90 100 db interchannel gain mismatch 0.2 0.5 db dc accuracy gain drift 100 - ppm/ c gain pin = ?l? 1.85 2 2.15 vrms output voltage ( note 5 ) gain pin = ?h? 2.35 2.5 2.65 vrms load capacitance ( note 6 ) 25 pf load resistance 5 k power supplies power supply current: ( note 7 ) normal operation (pdn pin = ?h?, fs 96khz) vdd hvee normal operation (pdn pin = ?h?, fs=192khz) vdd hvee power-down mode (pdn pin = ?l?) ( note 8 ) vdd hvee 22 6 25 6 10 10 30 9 33 9 100 100 ma ma ma ma a a note 2. measured by audio precision (system two). gain pin = ?l?. refer to the evaluation board manual regarding the measurement results. note 3. 98db at 16bit data note 4. s/n ration does not depend on the input data length note 5. full-scale voltage (0db). output voltage is proportional to vdd voltage. aout (typ.@ 0db, gain = 0db) = 2vrms vdd/5. note 6. when the output pin drives a capacitive load, a resistor should be a dded in series betw een output pin and capacitive load. note 7. these values are supplied to vdd pin or hvee pin. note 8. p/s pin is tied to vdd and the other all digital inputs including clock pins (mclk, bick and lrck) are tied to vdd or vss.
[AK4340] ms0501-e-01 2010/09 - 6 - filter characteristics (ta = 25 c; vdd = +4.5 +5.5v, hvee = -13.2 -4.5v; fs = 44.1khz, dem = off) parameter symbol min typ max units digital filter passband 0.05db ( note 9) -6.0db pb 0 - 22.05 20.0 - khz khz stopband ( note 9 ) sb 24.1 khz passband ripple pr 0.02 db stopband attenuation sa 54 db group delay ( note 10 ) gd - 19.3 - 1/fs digital filter + lpf frequency response 20.0khz 40.0khz 80.0khz fs=44.1khz fs=96khz fs=192khz fr fr fr - - - 0.05 0.05 0.05 - - - db db db note 9. the passband and stopband frequencies scale with fs (system sampling rate). for example, pb=0.4535fs (@ 0.05db), sb=0.546fs. note 10. delay time caused by digital filtering. this time is from setting the 16/24bit data of both channels to input register to the output of analog signal. dc characteristics (ta=25 c; vdd = +4.5 +5.5v, hvee = -13.2 -4.5v) parameter symbol min typ max units high-level input voltage low-level input voltage vih vil 2.2 - - - - 0.8 v v input leakage current ( note 11 ) iin - - 10 a note 11. p/s pin is pulled-up internally. (typ. 100k )
[AK4340] ms0501-e-01 2010/09 - 7 - switching characteristics (ta=25 c; vdd = +4.5 +5.5v, hvee = -13.2 -4.5v) parameter symbol min typ max units master clock frequency duty cycle fclk dclk 2.048 40 11.2896 36.864 60 mhz % lrck frequency normal speed mode double speed mode quad speed mode duty cycle fsn fsd fsq duty 8 60 120 45 48 96 192 55 khz khz khz % audio interface timing bick period normal speed mode double speed mode quad speed mode bick pulse width low pulse width high bick rising to lrck edge ( note 12 ) lrck edge to bick rising ( note 12 ) sdti hold time sdti setup time tbck tbck tbck tbckl tbckh tblr tlrb tsdh tsds 1/128fsn 1/64fsd 1/64fsq 30 30 20 20 20 20 ns ns ns ns ns ns ns ns ns control interface timing cclk period cclk pulse width low pulse width high cdti setup time cdti hold time csn high time csn ? ? to cclk ? ? cclk ? ? to csn ? ? tcck tcckl tcckh tcds tcdh tcsw tcss tcsh 200 80 80 40 40 150 50 50 ns ns ns ns ns ns ns ns reset timing pdn pulse width ( note 13 ) tpd 150 ns note 12. bick rising edge must not occur at the same time as lrck edge. note 13. the AK4340 can be reset by bringing pdn pin = ?l?.
[AK4340] ms0501-e-01 2010/09 - 8 - timing diagram 1/fclk tclkl vih tclkh mclk vil dclk=tclkh x fclk, tclkl x fclk 1/fs vih lrck vil tbck tbckl vih tbckh bick vil figure 1. clock timing tlrb lrck vih bick vil tsds vih sdti vil tsdh vih vil tblr figure 2. serial interface timing
[AK4340] ms0501-e-01 2010/09 - 9 - tcss csn vih cclk vil vih cdti vil vih vil c1 c0 r/w a4 tcckl tcckh tcds tcdh figure 3. write command input timing csn vih cclk vil vih cdti vil vih vil d3 d2 d1 d0 tcsw tcsh figure 4. write data input timing tpd vil pdn figure 5. power-down timing
[AK4340] ms0501-e-01 2010/09 - 10 - operation overview system clock the AK4340 requires mclk, bick and lrck external clocks. the master clock (mclk) should be synchronized with lrck but the phase is not critical. the mclk is used to operate the digital interpolation filter and the delta-sigma modulator. there are two methods to set mclk frequency. in manual setting mode (acks = ?0?: register 00h), the sampling speed is set by dfs0/1 ( table 1 ). the frequency of mclk at each sa mpling speed is set automatically. ( table 2 ) after exiting reset (pdn pin = ? ?), the AK4340 is in auto setting mode. in auto setting mode (acks = ?1?: default), as mclk frequency is detected automatically ( table 3 ), and the internal master clock becomes the appropriate frequency ( table 4 ), it is not necessary to set dfs0/1. in parallel control mode, the sampling speed can be set by only acks pin. the internal dfs0 and dfs1 bits are fixed to ?0?. therefore, when acks pin is ?l?, the AK4340 operates in normal speed mode. the AK4340 operates in auto setting mode at acks pin = ?h?. in parallel contro l mode, the AK4340 does not support 128fs and 192fs of double speed mode. all external clocks (mclk, bick and lrck) should always be present whenever the AK4340 is in the normal operation mode (pdn pin = ?h?). if these clocks are not provided, the AK4340 may draw excess current and may fall into unpredictable operation. this is because the device utilizes dynamic refreshed logic in ternally. the AK4340 should be reset by pdn pin = ?l? after threse clocks are provided. if the external clocks are not present, the AK4340 should be in the power-down mode (pdn pin = ?l?). after exiting reset at power-up etc., the AK4340 is in the power-down mode until mclk and lrck are input. dfs1 dfs0 sampling rate (fs) 0 0 normal speed mode 8khz~48khz default 0 1 double speed mode 60khz~96khz 1 0 quad speed mode 120khz~192khz table 1. sampling speed (manual setting mode) lrck (khz) mclk(mhz) bick (mhz) dfs1 dfs0 sampling speed fs 128fs 192fs 256fs 384f s 512fs 768fs 1152fs 64fs 0 0 32.0 - - 8.1920 12.2880 16.3840 24.5760 36.8640 2.0480 0 0 44.1 - - 11.2896 16.9344 22.5792 33.8688 - 2.8224 0 0 normal 48.0 - - 12.2880 18.4320 24.5760 36.8640 - 3.0720 0 1 88.2 11.2896 16.9344 22.5792 33.8688 - - - 5.6448 0 1 double 96.0 12.2880 18.4320 24.5760 36.8640 - - - 6.1440 1 0 176.4 22.5792 33.8688 - - - - - 11.2896 1 0 quad 192.0 24.5760 36.8640 - - - - - 12.2880 table 2. system clock example (manual setting mode)
[AK4340] ms0501-e-01 2010/09 - 11 - mclk sampling speed 1152fs normal (fs=32khz only) 512fs 768fs normal 256fs 384fs double 128fs 192fs quad table 3. sampling speed (auto setting mode: default at serial control mode) lrck mclk (mhz) fs 128fs 192fs 256fs 384fs 512fs 768fs 1152fs sampling speed 32.0khz - - - - 16.3840 24.5760 36.8640 44.1khz - - - - 22.5792 33.8688 - 48.0khz - - - - 24.5760 36.8640 - normal 88.2khz - - 22.5792 33.8688 - - - 96.0khz - - 24.5760 36.8640 - - - double 176.4khz 22.5792 33.8688 - - - - - 192.0khz 24.5760 36.8640 - - - - - quad table 4. system clock example (auto setting mode) audio serial interface format data is shifted in via the sdti pin using bick and lrck input s. in serial control mode, five serial data mode can be selected by dif2-0 bits. (see table 5 ). in parallel control mode, two serial da ta mode can be selected by dif0 pin. (see table 6) in all modes the serial data is msb-first, 2?s comp liment format and is latched on the rising edge of bick. mode 2 can be used for 16/20 msb justified formats by zeroing the unused lsbs. mode dif2 dif1 dif0 sdti format bick figure 0 0 0 0 16bit lsb justified 32fs figure 6 1 0 0 1 20bit lsb justified 40fs figure 7 2 0 1 0 24bit msb justified 48fs figure 8 default 3 0 1 1 24bit i 2 s compatible 48fs figure 9 4 1 0 0 24bit lsb justified 48fs figure 7 table 5. audio data format in serial control mode mode dif0 sdti format bick figure 2 0 24bit msb justified 48fs figure 8 3 1 24bit i 2 s compatible 48fs figure 9 table 6. audio data format in parallel control mode
[AK4340] ms0501-e-01 2010/09 - 12 - sdti bick lrck sdti 15 14 6 5 4 bick 0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1 3 2 1 0 15 14 ( 32fs ) ( 64fs ) 014 1 15 16 17 31 0 1 14 15 16 17 31 0 1 15 14 0 15 14 0 mode 0 don?t care don?t care 15:msb, 0:lsb mode 0 15 14 6 5 4 3 2 1 0 lch data rch data figure 6. mode 0 timing sdti lrck bick ( 64fs ) 09 1 10 11 12 31 0 1 9 10 11 12 31 0 1 19 0 19 0 mode 1 don?t care don?t care 19:msb, 0:lsb sdti mode 4 23:msb, 0:lsb 20 19 0 20 19 0 don?t care don?t care 22 21 22 21 lch data rch data 8 23 23 8 figure 7. mode 1,4 timing lrck bick ( 64fs ) sdti 022 1 2 24 31 0 1 31 0 1 23:msb, 0:lsb 22 1 0 don?t care 23 lch data rch data 23 30 22 224 23 30 22 1 0 don?t care 23 22 23 figure 8. mode 2 timing
[AK4340] ms0501-e-01 2010/09 - 13 - lrck bick ( 64fs ) sdti 03 1 2 24 31 0 1 31 0 1 23:msb, 0:lsb 22 1 0 don?t care 23 lch data rch data 23 25 3 224 23 25 22 1 0 don?t care 23 23 figure 9. mode 3 timing de-emphasis filter a digital de-emphasis filter is availabl e for 32, 44.1 or 48khz sampling rates (tc = 50/15s) and is enabled or disabled with dem0 and dem1. in case of double speed and quad speed mode, the digital de-emphasis filter is always off. dem1 dem0 mode 0 0 44.1khz 0 1 off default 1 0 48khz 1 1 32khz table 7. de-emphasis filter control (normal speed mode) output volume the AK4340 includes channel independent digital output volumes (att) with 256 levels at linear step including mute. these volumes are in front of the dac and can attenuate the input data from 0db to ?48db and mute. when changing levels, transitions are executed via soft changes; thus no switching noise occurs during these transitions. the transition time of 1 level and all 256 levels is shown in table 8 . transition time sampling speed 1 level 255 to 0 normal speed mode 4lrck 1020lrck double speed mode 8lrck 2040lrck quad speed mode 16lrck 4080lrck table 8. att transition time
[AK4340] ms0501-e-01 2010/09 - 14 - output gain setting outputs level of aoutl/aoutr pin can be selected by gain pin. gain pin gain output level (vdd=5v) l 0db 2vrms (typ) h +1.94db 2.5vrms (typ) table 9. output level setting soft mute operation soft mute operation is performed in digital domain. when the smute bit (smute pin) goes to ?1?(?h?), the output signal is attenuated by - during att_data att transition time ( table 8 ) from the current att level. when the smute bit (smute pin) is returned to ?0? (?l?), the mute is cancelled and the output attenuation gradually changes to the att level during att_data att transition time. if the soft mute is cancelled before attenuating to - after starting the operation, the attenuation is discontinued and returned to att level by the same cycle. the soft mute is effective for changing the signal source without stopping the signal transmission. smute bit or smute pin a ttenuation att level - a out gd gd (1) (2) (3) (1) notes: (1) att_data att transition time ( table 8 ). for example, in normal speed mode, this time is 1020lrck cycles (1020/fs) at att_data=255. (2) the analog output corresponding to the digital input has a group delay, gd. (3) if the soft mute is cancelled before attenuating to - after starting the operation, the attenuation is discontinued and returned to att level by the same cycle. figure 10. soft mute function system reset the AK4340 should be reset once by bringing pdn pin = ?l? upon power-up. the AK4340 is powered up and the internal timing starts clocking by lrck ? ? after exiting reset and power down state by mclk. the AK4340 is in the power-down mode until mclk and lrck are input.
[AK4340] ms0501-e-01 2010/09 - 15 - power-down the AK4340 is placed in the power-down mode by br inging pdn pin ?l? and th e analog outputs are gnd. figure 11 shows an example of the system timing at the power-down and power-up. normal operation internal state pdn power-down normal operation gd gd ?0? data d/a out (analog) d/a in (digital) clock in mclk, lrck, bick (1) (3) (6) dzfl/dzfr external mute (5) (3) (1) mute on (2) (4) don?t care notes: (1) the analog output corresponding to digital input has the group delay (gd). (2) analog outputs are floating (hi -z) at the power-down mode. (3) click noise occurs at the edge of pdn signal. this noise is output even if ?0? data is input. (4) the external clocks (mclk, bick and lrck) can be stopped in the power-down mode (pdn = ?l?). (5) please mute the analog output externally if the click noise (3) influences system application. the timing example is shown in this figure. figure 11. power-down/up sequence example
[AK4340] ms0501-e-01 2010/09 - 16 - reset function when rstn=0, dac is powered down but the internal register values are not initialized. the analog outputs go to vcom voltage and dzf pin goes to ?h?. figure 12 shows the example of reset by rstn bit. internal state rstn bit digital block power-down normal operation gd gd ?0? data d/a out (analog) d/a in (digital) clock in mclk,lrck,bick (1) (3) external mute (3) (1) (2) normal operation internal rstn bit 2~3/fs (6) 3~4/fs (6) don?t care (4) mute on notes: (1) the analog output corresponding to digital input has the group delay (gd). (2) analog outputs go to vc om voltage (vdd/2). (3) click noise occurs at the edges(? ?) of the internal timing of rstn bit. this noise is output even if ?0? data is input. (4) the external clocks (mclk, bick and lrck) can be stopped in the reset mode (rstn = ?l?). (5) dzf pins go to ?h? when the rstn bit becomes ?0?, and go to ?l? at 2/fs after rstn bit becomes ?1?. (6) there is a delay, 3~4/fs from rstn bit ?0? to the internal rstn bit ?0?, and 2~3/fs from rstn bit ?1? to the internal rstn ?1?. figure 12. reset sequence example
[AK4340] ms0501-e-01 2010/09 - 17 - mode control interface some function of the AK4340 can be controlled by pins (parallel control mode) shown in table 10 . the serial control interface is enabled by the p/s pin = ?l?. internal registers may be written to 3-wire p interface pins, csn, cclk and cdti. the data on this interface consists of chip address (2bits, c1/0; fixed to ?01?), read/write (1bit; fixed to ?1?, write only), register address (msb first, 5bits) and control data (msb first, 8bits). the AK4340 latches the data on the rising edge of cclk, so data should clocked in on the falling edge. the writi ng of data becomes valid by csn ? ?. the clock speed of cclk is 5mhz (max). function parallel control mode serial control mode double sampling mode at 128/192fs x o de-emphasis x o smute o o 16/20/24bit lsb justified format x o table 10. function list (o: available, x: not available) pdn pin = ?l? resets the registers to their default values. when the state of p/s pin is changed, the AK4340 should be reset by pdn pin = ?l?. the internal timing circuit is reset by rstn bit, but the registers are not initialized. cdti cclk c1 0 1234567 8 9 10 11 12 13 14 15 d4 d5 d6 d7 a1 a2 a3 a4 r/w c0 a0 d0 d1 d2 d3 csn c1-c0: chip address (fixed to ?01?) r/w: read/write (fixed to ?1?, write only) a4-a0: register address d7-d0: control data figure 13. control i/f timing *the AK4340 does not support the read command and chip address. c1/0 and r/w are fixed to ?011? *when the AK4340 is in the power down mode (pdn pin = ?l?) or the mclk is not provided, writing into the control register is inhibited. register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 1 acks 0 0 dif2 dif1 dif0 pw rstn 01h control 2 0 0 0 dfs1 dfs0 dem1 dem0 smute 02h control 3 0 0 0 invl invr 0 0 0 03h lch att att7 att6 att5 att4 att3 att2 att1 att0 04h rch att att7 att6 att5 att4 att3 att2 att1 att0 notes: for addresses from 05h to 1fh, data must not be written. when pdn pin goes ?l?, the registers are initialized to their default values. when rstn bit goes ?0?, the only internal timing is reset and the registers are not initialized to their default values. all data can be written to the register even if pw or rstn bit is ?0?.
[AK4340] ms0501-e-01 2010/09 - 18 - register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 1 acks 0 0 dif2 dif1 dif0 pw rstn default 1 0 0 0 1 0 1 1 rstn: internal timing reset control 0: reset. all registers are not initialized. 1: normal operation when mclk frequency or dfs changes, the click noise can be reduced by rstn bit. pw: power down control 0: power down. all registers are not initialized. 1: normal operation dif2-0: audio data interface formats (see table 5 ) initial: ?010?, mode 2 acks: master clock frequency auto setting mode enable 0: disable, manual setting mode 1: enable, auto setting mode master clock frequency is detected au tomatically at acks bit ?1?. in this case, the settings of dfs1-0 are ignored. when this bit is ?0?, dfs1-0 set the sampling speed mode. addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h control 2 0 0 0 dfs1 dfs0 dem1 dem0 smute default 0 0 0 0 0 0 1 0 smute: soft mute enable 0: normal operation 1: dac outputs soft-muted dem1-0: de-emphasis response (see table 7 ) initial: ?01?, off dfs1-0: sampling speed control 00: normal speed mode 01: double speed mode 10: quad speed mode when changing between normal/double speed mode and quad speed mode, some click noise occurs.
[AK4340] ms0501-e-01 2010/09 - 19 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h control 3 0 0 0 invl invr 0 0 0 default 0 0 0 0 0 0 0 0 invr: inverting lch output polarity 0: normal output 1: inverted output invl: inverting rch output polarity 0: normal output 1: inverted output addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h lch att att7 att6 att5 att4 att3 att2 att1 att0 04h rch att att7 att6 att5 att4 att3 att2 att1 att0 default 1 1 1 1 1 1 1 1 att = 20 log 10 (att_data / 255) [db] 00h: mute
[AK4340] ms0501-e-01 2010/09 - 20 - system design figure 14 and figure 15 show the system connection diagram. an evaluation board (akd4340) is available in order to allow an easy study on the layout of a surround circuit. mclk 1 bick 2 sdti 3 lrck 4 pdn 5 csn 6 cclk 7 cdti 8 gain 16 p/s 15 vdd 14 vss 13 hvee 12 aoutl 11 aoutr 10 nc 9 master clock p AK4340 fs 24bit audio data reset & power down 64fs 10u 0.1u + rch out lch out analog ground digital ground +5v analog supply + 10u 0.1u negative analog supply figure 14. typical connection diagram (serial control mode, gain=0db) mclk 1 bick 2 sdti 3 lrck 4 pdn 5 smute 6 a cks 7 dif0 8 gain 16 p/s 15 vdd 14 vss 13 hvee 12 aoutl 11 aoutr 10 nc 9 master clock mode setting AK4340 fs 24bit audio data reset & power down 64fs 10u 0.1u + rch out lch out analog ground digital ground +5v analog supply + 10u 0.1u negative analog supply figure 15. typical connection diagram (parallel control mode, gain=0db) notes: - lrck = fs, bick = 64fs. - when aout drives some capacitive load, some resi stor should be added in series between aout and capacitive load. - all input pins except for pull-up pin must not be left floating.
[AK4340] ms0501-e-01 2010/09 - 21 - 1. grounding and power supply decoupling vdd, hvee and vss are supplied from analog supply and should be separated from system digital supply. decoupling capacitor, especially 0.1 f ceramic capacitor for high frequency should be placed as near to vdd and hvee as possible. the differential voltage between vdd and vss pins set the analog output range. power-up sequence between vdd and hvee is not critical. 2. analog outputs the analog outputs are single-ended and centered around the ground (vss). the output signal range is typically 2vrms (@vdd=5v & gain pin = ?l?). the phase of the analog outputs can be inverted channel independently by invl/invr bits. the internal switched cap acitor filter (scf) and continuous time filter (c tf) attenuate the noise generated by the delta-sigma modulator beyond the audio passband. if the noise generated by the delta-sigma modulator beyond the audio band would be the problem, the 1 st order filter is required. (see figure 16 ) the output voltage is a positive full scale for 7fffffh (@ 24bit) and a negative full scale for 800000h (@24bit). the ideal output is 0v(vss) for 000000h (@24bit). 470 2.2n aout analog out figure 16. external 1 st order lpf circuit example (fc = 154khz, gain = -0.28db @ 40khz, gain = -1.04db @ 80khz)
[AK4340] ms0501-e-01 2010/09 - 22 - package 0-10 detail a seating plane 0.10 0.17 0.05 0.22 0.1 0.65 *5.0 0.1 1.1 (max) a 1 8 9 16 16pin tssop (unit: mm) *4.4 0.1 6.4 0.2 0.5 0.2 0.1 0.1 note: dimension "*" does not include mold flash. 0.13 m package & lead frame material package molding compound: epoxy lead frame material: cu lead frame surface treatme nt: solder (pb free) plate
[AK4340] ms0501-e-01 2010/09 - 23 - marking akm 4340et xxyyy 1) pin #1 indication 2) date code : xxyyy (5 digits) xx: lot# yyy: date code 3) marketing code : 4340et 4) asahi kasei logo date (yy/mm/dd) revision reason page contents 06/04/24 00 first edition 10/09/28 01 specification change 22 package the package dimension was changed. revision history
[AK4340] ms0501-e-01 2010/09 - 24 - important notice z these products and their specifications are subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized distributors as to current status of the products. z descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application exampl es of the semiconductor products. you are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your e quipments. akm assumes no responsibility fo r any losses incurred by you or third parties arising from the use of these information herein. akm assumes no liability for infringement of any patent, intellectual property, or other rights in the applica tion or use of such information contained herein. z any export of these products, or devices or systems containi ng them, may require an export license or other official approval under the law and regulations of the country of e xport pertaining to customs and tariffs, currency exchange, or strategic materials. z akm products are neither intended nor aut horized for use as critical components note1 ) in any safety, life support, or other hazard related device or system note2 ) , and akm assumes no responsibility fo r such use, except for the use approved with the express written consent by representative director of akm. as used here: note1 ) a critical component is one whose failure to functi on or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2 ) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aeros pace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akm products , who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above conten t and conditions, and the buyer or distributor agrees to assume any and all responsib ility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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